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Alif Semiconductor /AE722F80F55D5LS_CM55_HP_View /DSI /DSI_PHY_TST_CTRL0

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Interpret as DSI_PHY_TST_CTRL0

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PHY_TESTCLR)PHY_TESTCLR 0 (PHY_TESTCLK)PHY_TESTCLK

Description

PHY Test Interface Control Register 0

Fields

PHY_TESTCLR

PHY test interface clear (active-high).
PHY_TESTCLK

This bit is used to clock the TESTDIN bus into the D-PHY.

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Register License

THIS SOFTWARE IS PROVIDED “AS IS”. NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. ALIF SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data